Technical Field
The present disclosure relates to integrated circuit devices and, in particular, to transistors in a static random access memory array.
Description of the Related Art
The cost of manufacturing an integrated circuit (IC) is related to the number of process steps required to fabricate the IC. Reducing the number of process steps required to fabricate an IC may reduce the cost of manufacturing the IC in a number of ways. For example, reducing the number of process steps may decrease the duration of the fabrication process, thereby freeing up expensive resources, such as fabrication facilities and equipment, for use in the fabrication of additional ICs. As another example, reducing the number of process steps may increase the yield of the fabrication process, thereby reducing the cost per IC.
As semiconductor feature sizes have continued to shrink, conventional field-effect transistors (FETs) have increasingly suffered from problems such as short-channel effects, high leakage current, and high static power dissipation. Many alternatives to the conventional planar FET structure have been studied, including the non-planar finFET. A finFET is a field-effect transistor in which a portion of the transistor's semiconductor material forms a fin-like structure. Relative to conventional planar FETs, a finFET may exhibit reduced short-channel effects, leakage current, and/or static power dissipation.
Methods of fabricating finFETs on integrated circuits are known. For example, a conventional finFET fabrication process may include the following steps: formation and filling of trenches between the finFET and other semiconductor devices for shallow-trench isolation; removal of portions of the semiconductor substrate to form a fin; formation of sidewall spacers for a dummy gate; formation of the dummy gate to shield the body of the finFET from the dopants; implantation of dopants into the finFET's source and drain regions; annealing of the integrated circuit to activate the dopants; removal of the dummy gate; and formation of the real finFET gate between the spacers, so that the gate aligns with the finFET's undoped body region. During implantation of dopants, the dummy gate may shield the body of the finFET from the dopants.